Parity checking circuits generally comprise Exclusive OR or Exclusive OR circuits, as described in an article entitled "Parity Check Circuit Arrangement for Random Access Memory Array" by C. Marzin et al., published in the IBM Technical Disclosure Bulletin, Vol. 18, No. 5, October 1975, pages 1411-1421.
The parity checking circuit described in said article comprises four stages of two-input Exclusive OR circuits. Since each stage introduces some delay, the checking operation performed by this circuit is a comparatively lengthy process.
One may also use a network of three-input Exclusive OR circuits of the type described in French patent application No. 74 43620 filed in France by the present applicant on Dec. 31, 1974, publication No. 2 296 969. However, three-input Exclusive OR circuits require many components since the Exclusive OR function (.sym.) of three inputs, A,B,C, which is written: EQU A.sym.B.sym.C=ABC+ABC+ABC+ABC
necessitates four AND circuits and four OR circuits as well as complement-value generating circuits, all of which take much space. Consequently, the elimination of a logic stage entails an increase of the space occupied by the circuit.
Numerous Exclusive OR circuits having two, three and four inputs are known to the art. In this regard reference is made to the following U.S. patent application, U.S. patent and IBM Technical Disclosure Bulletin publications:
U.S. patent application Ser. No. 108,323, entitled "Dynamically Switchables Logic Block For JK/EOR Functions" by Jerry R. Case, filed Dec. 31, 1979, granted as U.S. Pat. No. 4,328,435 on May 4,1982. PA1 U.S. Pat. No. 3,129,406 entitled "Digital Signal Comparison Circuit" granted Apr. 14, 1964 to R. Perley; PA1 "Gated Two-Way Exclusive `OR` Trigger" by O. J. Bedrij, Vol. 2, No. 6, April 1970, page 51; PA1 "Exclusive `OR` Circuit" by R. C. Greenhalgh, Vol. 2, No. 6, April 1960, pages 98-99; PA1 "Three-Level Exclusive OR" by W. H. McAnney, Vol. 4, No. 7, December 1961, pages 58-59; PA1 "Exclusive OR Shift Circuit" by J. W. Delmege, Jr., Vol. 5, No. 1, June 1962, page 63; PA1 "Three Transistor Exclusive OR Circuit" by L. J. Patterson, Vol. 5, No. 8, January 1963, pages 38-39; PA1 "One Transistor, Exclusive OR Circuit" by I. G. Akmenkalns, Vol. 5, No. 12, May 1963, pages 65-66; PA1 "Two-Level Not Exclusive OR" by L. J. Boland, Vol. 7, No. 9, February 1965, pages 743-744; PA1 "Logic Level Equal-Compare Circuit" by L. J. Wallace, Vol. 8, No. 2, July 1965, page 330; PA1 "Exclusive-OR Circuit" by A. Kuck et al., Vol. 8, No. 4, September 1965, page 672; PA1 "Inverse Exclusive-OR Circuit" by T. S. Jen, Vol. 8, No. 8, January 1966, pages 1156-1157; PA1 "Exclusive-OR Circuit" by D. W. Murphy Vol. 8, No. 11, April 1966, page 1660; PA1 "Exclusive-OR Complement Circuit" by P. J. Evans, Vol. 9, No. 9, February 1967, pages 1210-1211; PA1 "Parallel-Reset Shift Register With Exclusive-OR Latches" by J. J. Kennedy, et al., Vol. 11, No. 9, February 1969, pages 1133-1134; PA1 "Four-Way Exclusive-OR" by J. E. Gersbach, Vol. 11, No. 9, February 1969, pages 1162-1163; PA1 "Exclusive-OR Logic" by R. T. Sha, Vol. 12, No. 8, January 1970, pages 1287-1288; PA1 "Exclusive-OR Circuit" by J. Villejoubert, Vol. 12, No. 9, February 1970, page 1469; PA1 "Integrated Circuit Exclusive-Or Circuit" by W. Rosenbluth, Vol. 12, No. 11, April 1970, page 1766; PA1 "Exclusive-OR Circuit" by J. A. Palmieri et al., Vol. 13, No. 5, October 1970, page 1074; PA1 "Bootstrap FET `OR` Circuit" by W. M. Smith, Jr., Vol. 13, No. 7, December 1970, page 1815; PA1 "Exclusive OR Data Manipulation For Cyclic Code Generation" by J. D. Dixon, Vol. 14, No. 3, August 1971, page 857; PA1 "Exclusive OR Set Latch" by C. W. Hannaford, Vol. 14, No. 9, February 1972, pages 2827-2828; PA1 "Dynamic FET Half-Cycle Delay Exclusive OR Circuit" by S. C. Pi, Vol. 14, No. 12, May 1972, page 3648; PA1 "Two-Way Exclusive `OR` Using Complementary FETs" by S. P. Bennett, Vol. 16, No. 3, August 1973, page 1007; PA1 "Exclusive OR Circuit (XOR)" by G. J. Gaudenzi, Vol. 16, No. 10, March 1974, page 3249; PA1 "Inverse Exclusive OR Circuit For Dynamic Logic" by L. R. Lau et al., Vol. 17 , No. 6, November 1974, pages 1666-1667; PA1 "Odd/Even Shunt Circuits" by M. P. Marcus, Vol. 17, No. 8, January 1975, pages 2234-2236; PA1 "Exclusive OR Invert Circuit" by P. Debord et al., Vol. 18, No. 1, June 1975, Page 137; PA1 "Parity Check Circuit Arrangement For Random-Access Memory Array" by C. Marzin et al., Vol. 18, No. 5, October 1975, pages 1411-1412; PA1 "Four-Bit Exclusive OR Circuit" by J. C. Leininger, Vol. 18, No. 6, November 1975, pages 1681-1682; PA1 "Antisaturation Clamp For XOR Circuit" by D. Swietek, Vol. 18, No. 8, January 1976, page 2508; PA1 "Logical Circuit" by Y. M. Ting, Vol. 18, No. 9, February 1976, page 2882; PA1 "Single-Cell Exclusive OR Circuit" by E. B. Eichelberger et al., Vol. 18, No. 9, February 1976, pages 2892-2893; "Exclusive OR Circuit" by A. A. Hansen, Vol. 19, No. 4, September 1976, pages 1235-1236; PA1 "Bubble Domain Exclusive OR Gate" by H. J. Yu, Vol. 19, No. 5, October 1976, pages 1932-1933; PA1 "MTL Exclusive OR Circuit" by G. J. Robbins, Vol. 19, No. 6, November 1976, page 2077; PA1 "Gated Exclusive OR Circuit" by F. H. Lohrey et al., Vol. 19, No. 6, November 1976, page 2080; PA1 "Cascode Exclusive OR" by J. E. Gersbach, Vol. 19, No. 6, November 1976, pages 2010-2011; PA1 "T.sup.2 L Exclusive OR" by F. Montegari, Vol. 19, No. 9, February 1977, page 3430; PA1 "Exclusive OR Circuit Conditioned by A Plurality of Gates" by J. Brandon, Vol. 19, No. 10, March 1977, pages 3761-3762; PA1 "Exclusive OR Input Decoders For PLA" by P. S. Balasubramanian et al., Vol. 20, No. 6, November 1977, pages 2308-09; PA1 "Exclusive OR Output Latch For PLA" by P. S. Balasubramanian et al., Vol. 20, No. 6, November 1977, pages 2310-2311; PA1 "4-Way Exclusive OR" by A. Weinberger, Vol. 20, No. 8, January 1978, pages 3220-3222; PA1 "Three-Device Exclusive OR Circuit" by P. S. Balasubramanian et al., Vol. 20, No. 10, March 1978, pages 4014-4015; PA1 "Inverted XOR Circuit" by A. Brunin, Vol. 21, No. 5, October 1978, page 1913; PA1 "Error Detecting Circuit For Open Input Terminals" by G. A. Maley et al., Vol. 21, No. 7, December 1978, pages 2806-2808; PA1 "Summing of Exclusive-OR Terms Having a Common Factor by Converting To a Single XOR" by A. Weinberger, Vol. 22, No. 1, June 1979, pages 234-236; PA1 "Exclusive OR Circuit" by A. Y. Chang et al., Vol. 22, No. 2, July 1979, pages 593-594; PA1 "High Speed exclusive-OR Circuit" by R. L. Ehrlickman, Vol. 22, No. 6, November 1979, page 2291; PA1 "Exclusive OR Circuit" by Z. T. Dearden et al., Vol. 23, No. 2, July 1980, pages 684-685; PA1 "Bipolar Selector Functions" by R. T. Dennison et al., Vol. 23, No. 5, October 1980, pages 1913-1914; PA1 "NPN-PNP Exclusive OR" by F. A. Montegari, Vol. 23, No. 10, March 1981, page 4502.
IBM Technical Disclosure Bulletin publications: